SPI0 interrupt status
| RXTH | Receive FIFO Threshold. When 1, the receive FIFO threshold has been reached, and the related interrupt is enabled. |
| TXTH | Transmit FIFO Threshold. When 1, the transmit FIFO threshold has been reached, and the related interrupt is enabled. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXTIMEOUT | Receive Timeout. When 1, the receive FIFO has timed out, based on the timeout configuration in the CFGSPI register, and the related interrupt is enabled. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| BUSERR | Bus Error. This is simply a copy of the same bit in the STATSPI register. The bus error interrupt is always enabled. |
| RXEMPTY | Receive FIFO Empty. This is simply a copy of the same bit in the STATSPI register. |
| TXEMPTY | Transmit FIFO Empty. This is simply a copy of the same bit in the STATSPI register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| RXCOUNT | Receive FIFO Count. This is simply a copy of the same field in the STATSPI register, included here so an ISR can read all needed status information in one read. |
| TXCOUNT | Transmit FIFO Available. This is simply a copy of the same field in the STATSPI register, included here so an ISR can read all needed status information in one read. |